• GATEline, kvalite sedan 1984

  • Schemakonstruktion

  • Simulering

  • Mönsterkortskonstruktion

  • Signalintegritet

  • PLM-system

JTAG för Design for Test i OrCAD Capture

Måndag 21 november 2016

OrCAD® Capture has been enhanced to now include XJTAG DFT Assistant, an easy-to-use interface that significantly increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design system. Developed by boundary-scan hardware and software tool supplier XJTAG, XJTAG DFT Assistant allows users to detect and correct JTAG errors at the design stage before the PCB is produced, preventing costly re-spins and project delays.